Low input-output offset bus buffers for ATCA

Are you one of those IPMB/I²C designers that realize the I²C message isn't getting through
in your ATCA system?

Did you know the IES5501 I²C bus buffer has only 30mV of input-output offset and has I²C compliant switching levels?….

And the IES5501 bus buffer IC now makes an analog radial (star) system the preferred choice, lowering the cost of high performance radial systems…..

IES5501 I²C bus buffer typically has only 30mV of input-output offset (guaranteed < 60mV)

Bi-directional bus buffers don’t receive information to set the data direction flow. To ensure latching doesn’t occur (one of an I²C designer’s worst enemies) the output voltage on the data lines must be larger than the input voltage.

Many buffers including the P82B96 use ‘fixed’ input and output voltages. If the P82B96 bus buffer input signal is below 0.5V the output is set at 0.6V.

The IES5501 is different and creates an ultra-low ‘input-output offset’ voltage using unique analog design principles. The IES5501 thus ensures the output is typically only 30mV larger than its input.

If the input to the IES5501 is equal to or less than 30% of the supply voltage, the output will be equal to the input plus typically only 30mV (60mV is worst case). And with a power supply of 3.3V, the IES5501 will still be able to accept an input of up to 0.99V.

IES5501 has I²C compliant switching levels

All compliant I²C devices are required to have a low level output voltage below 0.4V. When a device isn’t compliant with the I²C specification its performance in a system can be affected because of smaller safety margins (also known as ‘noise’ margin).

Many bus buffers do not meet this specification because of their fixed input-output offsets. The IES5501 is I²C compliant with the low-level requirements of I²C and its output will also be compliant (provided input levels are kept just below the specification).

In the worst-case scenario for I²C level compliance, the IES5501 will still be able to output 0.4V even if the input is 0.34V.

Table 1: I²C Bus Specification Characteristics of the SDA and SCL I/O stages
Source I²C Bus Specification and User Manual, p36, NXP Semiconductors 2007

Symbol
Parameter
Conditions
Standard Mode
V IL
LOW-level input voltage

-0.5 V
0.3 VDD
VIH
HIGH level input voltage

0.7 VDD

VOL1
LOW-level outout voltage (open drain or open collector) at 3mA sink current
VDD > 2 V
0
0.4 V
VOL3
LOW-level outout voltage (open drain or open collector) at 3mA sink current
VDD < 2 V
N/A
N/A

Using the IES5501 and IES5502 Bus Buffers in a Fully Radial AdvancedTCA System

The following is an extract from the AN103 application note about using the IES5501 and IES5502 bus buffers in AdvancedTCA systems.

Figure 7 shows the use of the IES5501 and IES5502 I²C compliant buffers in a radial AdvancedTCA implementation. Bi-directional Analog Switches are used on the Shelf Manager to allow one IES5501 I²C bus buffer to serve 2 FRU’s. It is unlikely that this AdvancedTCA implementation will have a total capacitance above 250pF and so no Rise Rate Accelerator is required on the backplane side of the IES5501. The total capacitance on the bus from the Shelf Manager microprocessor that drives just 12 buffers is unlikely to exceed 100pF and therefore no Rise Rate Accelerator is required. Again, the IES5502 is used as the buffer on the FRU.

ATCA Fig 7

Another valid Fully Radial AdvancedTCA implementation is to simply use 24 IES5501’s on the Shelf Manager as shown in Figure 12.

The following waveforms show the IPMB signals at specified points in the fully Radial AdvancedTCA implementation when using one IES5501 to serve two bi-directional analog switches (FET switches). The circuitry in figure 8 is used to capture the waveforms in figures 9, 10 and 11. Both the rising and falling edges are shown. When no FET switch is enabled, the output of the FET switch is undefined and the output of the IES5501 on the FRU is pulled high (shown in figure 9). Figure 10 and 11 show the signals when one FET switch and two FET switches are enabled respectively. In both these cases it can be seen that the IPMB rise time requirement of 900ns (from 1V to 2.3V for Vcc = 3.3V) is easily met.